The goal of this project is to predict which design Verilog simulation fails are from an actual design bug vs. an invalid simulation artifact or bad checking assumption. The sponsor will provide the complete historic data set of Verilog simulation results from a recent x86 Core design project, consisting of possibly millions of design simulations and the simulation attributes and their results and log data. The design project should use machine learning algorithms to process the historic data and create an accurate prediction model to determine which simulation fails will be the result of a design bug. The project should also study and determine which simulation attributes and log data info actually provide value to the prediction accuracy and only use the minimum set of these. The quality of this design project should be measured on the accuracy of prediction when the model is run across the historic dataset.